A 3D mixed-mode ESD protection circuit simulation-design methodology

被引：9
|
作者：
Xie, H [1 ]
Zhan, R [1 ]
Feng, H [1 ]
Chen, G [1 ]
Wang, A [1 ]
Gafiteanu, R [1 ]
机构：
[1] IIT, Dept Elect & Comp Engn, Integrated Elect Lab, Chicago, IL 60616 USA
来源：
PROCEEDINGS OF THE IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2004年
关键词：
D O I：
10.1109/CICC.2004.1358788
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Electrostatic discharge (ESD) is a serious IC reliability problem. On-chip ESD protection are used to protect ICs against ESD damages. [1] This paper presents a real 3D mixed-mode ESD protection circuit simulation-design methodology for ESD design prediction. Practical ESD protection design examples in 0.35mum BiCMOS are given.
引用
下载
收藏
页码：243 / 246
页数：4
相关论文
共 50 条
  • [1] Mixed-mode ESD protection circuit simulation-design methodology
    Feng, H
    Wu, Q
    Chen, G
    Guan, X
    Xie, H
    Wang, AZ
    Zhan, R
    PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL IV: DIGITAL SIGNAL PROCESSING-COMPUTER AIDED NETWORK DESIGN-ADVANCED TECHNOLOGY, 2003, : 652 - 655
  • [2] A mixed-mode ESD protection circuit simulation-design methodology
    Feng, HG
    Chen, G
    Zhan, RY
    Wu, Q
    Guan, XK
    Xie, HL
    Wang, AZH
    Gafiteanu, R
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2003, 38 (06) : 995 - 1006
  • [3] Key aspects on ESD protection design for ICs: Mixed-mode simulation and RF/mixed-signal ESD
    Wang, A
    Feng, H
    Chen, G
    Zhan, R
    Xie, H
    Wu, Q
    Guan, X
    2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2003, : 1000 - 1005
  • [4] ESD protection design optimization using a mixed-mode simulation and its impact on ESD protection design of power bus line resistance
    Hayashi, H
    Kuroda, T
    Kato, K
    Fukuda, K
    Baba, S
    Fukuda, Y
    SISPAD: 2005 International Conference on Simulation of Semiconductor Processes and Devices, 2005, : 99 - 102
  • [5] ESD Design Verification Aided by Mixed-Mode Multiple-Stimuli ESD Simulation
    Di, Mengfu
    Pan, Zijin
    Li, Cheng
    Wang, Albert
    IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2021, 9 : 1194 - 1201
  • [6] CONFIDENCE IN MIXED-MODE CIRCUIT SIMULATION
    BROWN, AD
    ZWOLINSKI, M
    NICHOLS, KG
    KAZMIERSKI, TJ
    COMPUTER-AIDED DESIGN, 1992, 24 (02) : 115 - 118
  • [7] Design of CMOS transistors to maximize circuit FOM using a coupled process and mixed-mode simulation methodology
    Venugopal, R.
    Chakravarthi, S.
    Chidambaram, P. R.
    IEEE ELECTRON DEVICE LETTERS, 2006, 27 (10) : 863 - 865
  • [8] Mixed-mode simulation and analysis of 3D double gate junctionless nanowire transistor for CMOS circuit applications
    Baidya, Achinta
    Lenka, Trupti Ranjan
    Baishya, Srimanta
    SUPERLATTICES AND MICROSTRUCTURES, 2016, 100 : 14 - 23
  • [9] Voltage Regulators Design Through Advanced Mixed-Mode Circuit Simulation
    Bizzarri, F.
    Brambilla, A.
    Saggini, S.
    IEEE TRANSACTIONS ON POWER ELECTRONICS, 2014, 29 (09) : 4496 - 4499
  • [10] Method of mixed-mode circuit and device simulation
    Wang, Hui
    Luo, Jiong
    Qinghua Daxue Xuebao/Journal of Tsinghua University, 1996, 36 (09): : 88 - 94
12345