A 3D mixed-mode ESD protection circuit simulation-design methodology

被引：9
|
作者：
Xie, H [1 ]
Zhan, R [1 ]
Feng, H [1 ]
Chen, G [1 ]
Wang, A [1 ]
Gafiteanu, R [1 ]
机构：
[1] IIT, Dept Elect & Comp Engn, Integrated Elect Lab, Chicago, IL 60616 USA
来源：
PROCEEDINGS OF THE IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2004年
关键词：
D O I：
10.1109/CICC.2004.1358788
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Electrostatic discharge (ESD) is a serious IC reliability problem. On-chip ESD protection are used to protect ICs against ESD damages. [1] This paper presents a real 3D mixed-mode ESD protection circuit simulation-design methodology for ESD design prediction. Practical ESD protection design examples in 0.35mum BiCMOS are given.
引用
收藏
页码：243 / 246
页数：4
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