A 3D mixed-mode ESD protection circuit simulation-design methodology

被引：9

作者：

Xie, H ^{[1
]}

Zhan, R ^{[1
]}

Feng, H ^{[1
]}

Chen, G ^{[1
]}

Wang, A ^{[1
]}

Gafiteanu, R ^{[1
]}

机构：

[1] IIT, Dept Elect & Comp Engn, Integrated Elect Lab, Chicago, IL 60616 USA

来源：

PROCEEDINGS OF THE IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2004年

关键词：

D O I：

10.1109/CICC.2004.1358788

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Electrostatic discharge (ESD) is a serious IC reliability problem. On-chip ESD protection are used to protect ICs against ESD damages. [1] This paper presents a real 3D mixed-mode ESD protection circuit simulation-design methodology for ESD design prediction. Practical ESD protection design examples in 0.35mum BiCMOS are given.

引用

页码：243 / 246

页数：4

共 50 条

[41] Geometry of mixed-mode oscillations in the 3-D autocatalator
Milik, A
Szmolyan, P
Loffelmann, H
Groller, E
INTERNATIONAL JOURNAL OF BIFURCATION AND CHAOS, 1998, 8 (03): : 505 - 519
[42] 3-D Integration and ESD Protection: Design and Analysis
Mitra, Souvick
Gebreselasie, Ephrem
Li, You
Gauthier, Robert, Jr.
Thuy Tran-Quinn
Ramachandran, Koushik
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2016, 16 (04) : 497 - 503
[43] 3D Characterization of Mixed-Mode Fracture Toughness of Materials Using a New Loading Device
Oskui, Abuzar Es'haghi
Choupani, Naghdali
Shameli, Moharram
LATIN AMERICAN JOURNAL OF SOLIDS AND STRUCTURES, 2016, 13 (08): : 1464 - 1482
[44] Mixed-Mode Multidirectional Poisson's Ratio Modulation in Auxetic 3D Lattice Metamaterials
Mukhopadhyay, Tanmoy
Kundu, Diptiman
ADVANCED ENGINEERING MATERIALS, 2022, 24 (05)
[45] Reliability of ESD protection devices designed in a 3D technology
Courivaud, B.
Nolhier, N.
Ferru, G.
Bafleur, M.
Caignet, F.
MICROELECTRONICS RELIABILITY, 2014, 54 (9-10) : 2272 - 2277
[46] New Mixed-Mode Design Methodology for High-Efficiency Outphasing Chireix Amplifiers
Chang, Hsiu-Chen
Hahn, Yunsik
Roblin, Patrick
Barton, Taylor Wallis
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2019, 66 (04) : 1594 - 1607
[47] Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND flash memory
Ikehashi, T
Imamiya, K
Sakui, K
IEEE TRANSACTIONS ON ELECTRONICS PACKAGING MANUFACTURING, 2000, 23 (04): : 246 - 254
[48] Design Methodology for Transmission-Line Based (TMLB) Pi-Type ESD Protection Circuit
Lee, Jian-Hsing
Iyer, Natarajan Mahadeva
2020 IEEE INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA), 2020,
[49] Mixed Mode Simulation of Heavy Ion Impact on 3D SRAM Cell
Rathod, S. S.
Saxena, A. K.
Dasgupta, S.
2009 4TH INTERNATIONAL CONFERENCE ON COMPUTERS AND DEVICES FOR COMMUNICATION (CODEC 2009), 2009, : 171 - +
[50] A new design methodology using simulation for on-chip ESD protection designs for integrated circuits
Wang, AZ
Tsay, CH
1998 5TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY PROCEEDINGS, 1998, : 509 - 512

← 1 2 3 4 5 →