Analysis of gate-induced drain leakage characteristics and threshold voltage modulation of plasma-doped FinFETs for low-power applications

FinFET devices were fabricated using plasma doping both at the source and drain extensions and in the channel region. In an effort to overcome dopant loss after the strip process, oxide buffer layers were deposited prior to plasma doping. Owing to the oxide buffer, 76% of the dopants were retained after the strip process and even after ashing, thereby keeping a high doping concentration of over 1 x 10(20) atoms/cm(3) on the surface of the Si fin. The gate-induced drain leakage (GIDL) current was decreased by 2 orders of magnitude due to the shallow and abrupt plasma doping, compared to the performance with an ion implantation method. The threshold voltage (V-th) was shifted by 250 mV through plasma doping of the channel. The doping conformality was evaluated using electrical measurements and a newly-proposed method based on the GIDL data with various fin widths. The conformal doping profile with a smaller dopant loss provides a smaller GIDL current. (C) 2016 The Japan Society of Applied Physics