An 8-bit 120-MS/s Interleaved CMOS Pipeline ADC Based on MOS Parametric Amplification

被引：12

作者：

Oliveira, J. ^{[1
,2
]}

Goes, J. ^{[2
,3
]}

Figueiredo, M. ^{[1
,2
]}

Santin, E. ^{[1
,2
]}

Fernandes, J. ^{[4
]}

Ferreira, J. ^{[1
,2
]}

机构：

[1] Univ Nova Lisboa, Ctr Technol & Syst, Inst Dev New Technol CTS UNINOVA, P-2825114 Monte De Caparica, Portugal

[2] Univ Nova Lisboa, Dept Elect Engn, Fac Sci & Technol, P-2825114 Monte De Caparica, Portugal

[3] Silicon & Software Syst, P-2829516 Caparica, Portugal

[4] INESC ID, R&D IC Unit, P-1000029 Lisbon, Portugal

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2010年 / 57卷 / 02期

关键词：

Analog-to-digital converter (ADC); MOS parametric amplification; pipeline; time-interleaved; RESIDUE AMPLIFICATION;

D O I：

10.1109/TCSII.2009.2038632

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This brief presents an 8-bit 120-MS/s time-interleaved pipeline analog-to-digital converter (ADC) fully based on MOS discrete-time parametric amplification. The ADC, fabricated in a 130-nm CMOS logic process, features an active area below 0.12 mm(2), where only MOS devices are used. Measurement results for a 20-MHz input signal shows that the ADC achieves 39.7 dB of signal-to-noise ratio, 49.3 dB of spurious-free dynamic range, -47.5 dB of total harmonic distortion, 39.1 dB of signal-to-noise-plus-distortion ratio, and 6.2 bits of peak effective number of bits while consuming less than 14 mW from a 1.2-V supply.

引用

页码：105 / 109

页数：5

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