On the Thermal Attack in Instruction Caches

被引:15
|
作者
Kong, Joonho [1 ]
John, Johnsy K. [2 ]
Chung, Eui-Young [3 ]
Chung, Sung Woo [1 ]
Hu, Jie [4 ]
机构
[1] Korea Univ, Sci Lib, Div Comp & Commun Engn, Seoul 136713, South Korea
[2] Adv Micro Devices Inc, Boston Design Ctr, AMD Boston Design Ctr, Boxboro, MA 01719 USA
[3] Yonsei Univ, Sch Elect & Elect Engn, Seoul 120749, South Korea
[4] New Jersey Inst Technol, Dept Elect & Comp Engn, Newark Coll Engn, Newark, NJ 07102 USA
关键词
Cache memories; fine-grain localized hotspot; malicious codes; microprocessors; thermal attack; POWER;
D O I
10.1109/TDSC.2009.16
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The instruction cache has been recognized as one of the least hot units in microprocessors, which leaves the instruction cache largely ignored in on-chip thermal management. Consequently, thermal sensors are not allocated near the instruction cache. However, malicious codes can exploit the deficiency in this empirical design and heat up fine-grain localized hotspots in the instruction cache, which might lead to physical damages. In this paper, we show how instruction caches can be thermally attacked by malicious codes and how simple techniques can be utilized to protect instruction caches from the thermal attack.
引用
收藏
页码:217 / 223
页数:7
相关论文
共 50 条
  • [1] PROCEDURE MERGING WITH INSTRUCTION CACHES
    MCFARLING, S
    [J]. SIGPLAN NOTICES, 1991, 26 (06): : 71 - 79
  • [2] On the reliability of drowsy instruction caches
    Shin, Soong Hyun
    Chung, Sung Woo
    Jhon, Chu Shik
    [J]. ADVANCES IN COMPUTER SYSTEMS ARCHITECTURE, PROCEEDINGS, 2006, 4186 : 445 - 451
  • [3] Timing Analysis for Instruction Caches
    Frank Mueller
    [J]. Real-Time Systems, 2000, 18 : 217 - 247
  • [4] Timing analysis for instruction caches
    Mueller, F
    [J]. REAL-TIME SYSTEMS, 2000, 18 (2-3) : 217 - 247
  • [5] Precise control of instruction caches
    Smirli, M
    Lioupis, D
    Kissell, K
    [J]. FIFTH INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING, PROCEEDINGS, 1998, : 11 - 18
  • [6] An Instruction to Accelerate Software Caches
    Azevedo, Arnaldo
    Juurlink, Ben
    [J]. ARCHITECTURE OF COMPUTING SYSTEMS - ARCS 2011, 2011, 6566 : 158 - +
  • [7] Data-Out Instruction-In (DOIN!): Leveraging Inclusive Caches To Attack Speculative Delay Schemes
    Aimoniotis, Pavlos
    Kvalsvik, Amund Bergland
    Sjalander, Magnus
    Kaxiras, Stefanos
    [J]. 2022 IEEE INTERNATIONAL SYMPOSIUM ON SECURE AND PRIVATE EXECUTION ENVIRONMENT DESIGN (SEED 2022), 2022, : 49 - 60
  • [8] WCET analysis of instruction caches with prefetching
    Yan, Jun
    Zhang, Wei
    [J]. ACM SIGPLAN NOTICES, 2007, 42 (07) : 175 - 184
  • [9] WCET Analysis of Instruction Caches with Prefetching
    Yan, Jun
    Zhang, Wei
    [J]. LCTES'07: PROCEEDINGS OF THE 2007 ACM SIGPLAN-SIGBED CONFERENCE ON LANGUAGES, COMPILERS, AND TOOLS FOR EMBEDDED SYSTEMS, 2007, : 175 - 184
  • [10] ON THE DESIGN OF ON-CHIP INSTRUCTION CACHES
    MCCROSKY, C
    VENDERBUHS, B
    [J]. MICROPROCESSORS AND MICROSYSTEMS, 1988, 12 (10) : 563 - 572