CLOCKED SEMI-FLOATING-GATE ULTRA LOW-VOLTAGE CURRENT MULTIPLIER

被引：2

作者：

Berg, Y. ^{[1
]}

Mirmotahari, O. ^{[1
]}

机构：

[1] Univ Oslo, Dept Informat, N-0316 Oslo, Norway

来源：

2009 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1 AND 2 | 2009年

关键词：

CIRCUITS;

D O I：

10.1109/ECCTD.2009.5275022

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper we present a ultra low voltage current mode multiplier. The current multiplier is based on a clocked semi floating gate design strategy used for ultra low voltage digital and analog design. By imposing offsets to semi-floating-gate nodes the current level may be increased while maintaining a very low supply voltage. The offset voltages are used to shift the effective threshold voltage of the evaluating transistors. A current multiplier able to operate at supply voltages below 200mV is presented and simulated data are provided. The simulated data presented are obtained using the Spectre simulator provided by Cadence and valid for a 90nm CMOS process.

引用

页码：445 / 448

页数：4

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