Continuous time delta sigma modulators with reduced clock jitter sensitivity

被引：0

作者：

Zare-Hoseini, Hashern ^{[1
]}

Kale, Izzet ^{[1
,2
]}

机构：

[1] Univ Westminster, Appl DSP & VSLI Res Grp, Dept Elect Syst, London W1R 8AL, England

[2] Eastern Mediterranean Univ, Appl DSP & VSLI Res Grp, Gazimagusa, Cyprus

来源：

2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS | 2006年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a technique and method is presented to suppress the effect of clock-jitter in continuous-time delta-sigma modulators with switched-current (current-steering) digital to analogue converters. A behavioural, transistor-level and noise analysis are presented followed by circuit-level simulations. The proposed approach which is a switched-current type of digital to analogue conversion is fully compatible Kith CMOS processes and multi-bit operations which are Widely used in high speed applications. Moreover, having a pulse-shaped output signal does not introduce extra demands on the modulator and hence does not increase the modulator's power consumption. A third-order continuous-time Delta Sigma modulator with the proposed digital-to-analogue converter in its feedback was used for circuit-level simulations. Results proved the robustness of the technique in suppressing the clock-jitter effects.

引用

页码：5371 / +

页数：2

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