A Method for Measuring and Alleviating Clock-jitter in Continuous-Time Delta-Sigma Modulators

被引：0
|
作者：
Jiang, Yanfeng [1 ]
Zhang, Xiaobo [1 ]
Yang, Bing [1 ]
机构：
[1] N China Univ Technol, Dept Microelect, Coll Informat Engn, Beijing 100144, Peoples R China
来源：
ASCC: 2009 7TH ASIAN CONTROL CONFERENCE, VOLS 1-3 | 2009年
关键词：
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
Continuous-time Delta-Sigma modulators are able to operate at higher frequencies than their discrete-time counterparts. However, they suffer more severely from non-idealities such as clock jitter. A method for measuring this clock jitter has been proposed. Moreover, the effect of the non-ideality are explained and a continuous-time to discrete-time conversion method is presented in order to aid in the analysis of this effect. The SC-R feedback circuit has been presented here to help eliminate clock jitter noise.
引用
收藏
页码：567 / 570
页数：4
相关论文
共 50 条
  • [1] Fast clock-jitter simulation in continuous-time Delta-Sigma modulators
    Benabes, P
    Kielbasa, R
    [J]. IMTC/2001: PROCEEDINGS OF THE 18TH IEEE INSTRUMENTATION AND MEASUREMENT TECHNOLOGY CONFERENCE, VOLS 1-3: REDISCOVERING MEASUREMENT IN THE AGE OF INFORMATICS, 2001, : 1587 - 1590
  • [2] Clock-jitter reduction techniques in continuous time delta-sigma modulators
    Zare-Hoseini, Hashem
    Kale, Izzet
    [J]. 2006 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PAPERS, 2006, : 117 - 118
  • [3] Clock jitter and quantizer metastability in continuous-time delta-sigma modulators
    Cherry, James A.
    Martin Snelgrove, W.
    [J]. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1999, 46 (06): : 661 - 676
  • [4] Clock jitter and quantizer metastability in continuous-time delta-sigma modulators
    Cherry, JA
    Snelgrove, WM
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 1999, 46 (06) : 661 - 676
  • [5] Clock jitter noise spectra in continuous-time delta-sigma modulators
    Oliaei, O
    [J]. ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2: ANALOG AND DIGITAL CIRCUITS, 1999, : 192 - 195
  • [6] Fundamental limitations of continuous-time delta-sigma modulators due to clock jitter
    Reddy, Karthikeyan
    Pavan, Shanthi
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2007, 54 (10) : 2184 - 2194
  • [7] Fundamental limitations of continuous-time delta-sigma modulators due to clock jitter
    Reddy, Karthikeyan
    Pavan, Shanthi
    [J]. 2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS, 2006, : 2021 - +
  • [8] A simple technique to reduce clock jitter effects in continuous-time Delta-Sigma modulators
    Chang, Hairong
    Tang, Hua
    [J]. PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 2008, : 1870 - 1873
  • [9] A new method for elimination of the clock jitter effects in continuous time Delta-Sigma modulators
    Shamsi, H
    Shoaei, O
    Doost, R
    [J]. IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2005, E88A (10): : 2570 - 2578
  • [10] Analysis of Clock Jitter in Continuous-Time Sigma-Delta Modulators
    Vasudevan, Vinita
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2009, 56 (03) : 519 - 528
12345