Design of improved rail-to-rail low-distortion and low-stress switches in advanced CMOS technologies

被引：6
|
作者：
Galhardo, A. [1 ]
Goes, J. [2 ]
Paulino, N. [2 ]
机构：
[1] DEEA Inst Super Engn Lisboa, Lisbon, Portugal
[2] Univ Nova Lisboa, Fac Ciencias & Tecnol, DEE FCT UNL CTS UNINOVA, Monte De Caparica, Portugal
来源：
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2010年 / 64卷 / 01期
关键词：
Switch linearization; Reliability; Switched-capacitor linearization control circuit (SLC); Bootstrapped switch; Clock boosting; LOW-VOLTAGE;
D O I：
10.1007/s10470-009-9357-z
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper describes the efficient design of an improved and dedicated switched-capacitor (SC) circuit capable of linearizing CMOS switches to allow SC circuits to reach low distortion levels. The described circuit (SC linearization control circuit, SLC) has the advantage over conventional clock-bootstrapping circuits of exhibiting low-stress, since large gate voltages are avoided. This paper presents exhaustive corner simulation results of a SC sample-and-hold (S/H) circuit which employs the proposed and optimized circuits, together with the experimental evaluation of a complete 10-bit ADC utilizing the referred S/H circuit. These results show that the SLC circuits can reduce distortion and increase dynamic linearity above 12 bits for wide input signal bandwidths.
引用
收藏
页码：13 / 22
页数：10
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