Low-voltage, low-distortion and rail-to-rail CMOS sample and hold circuit

被引：1
|
作者：
Tanno, K [1 ]
Sato, K
Tanaka, H
Ishizuka, O
机构：
[1] Miyazaki Univ, Fac Engn, Miyazaki 8892192, Japan
[2] Miyakonojo Nalt Coll Technol, Dept Elect Engn, Miyakonojoshi 8858567, Japan
来源：
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES | 2005年 / E88A卷 / 10期
关键词：
sample hold circuit; low-voltage circuits; boost circuits; MOS analog integrated circuits; analog circuits;
D O I：
10.1093/ietfec/e88-a.10.2696
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this letter, we propose a sample and hold circuit (S/H circuit) with the clock boost technique and the input signal tracking technique. The proposed circuit block generates the clock with the amplitude Of V-DD + nu(in), and the clock is used to control the MOS switch. By applying this circuit to a S/H circuit, we can deal with the rail-to-rail signal with maintaining low distortion. Furthermore, the hold error caused by the charge injection and the clock feedthrough can be also reduced by using the dummy switch. The Star-HSPICE simulation results are reported in this letter.
引用
收藏
页码：2696 / 2698
页数：3
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