Spectre attack detection with Neutral Network on RISC-V processor

被引:0
|
作者
Anh-Tien Le [1 ]
Trong-Thuc Hoang [1 ]
Ba-Anh Dao [1 ]
Tsukamoto, Akira [2 ]
Suzaki, Kuniyasu [3 ]
Cong-Kha Pham [1 ]
机构
[1] Univ Electrocommun, Tokyo, Japan
[2] Natl Inst Adv Ind Sci & Technol, Tokyo, Japan
[3] Technol Res Assoc Secure IoT Edge Applicat Based, Tokyo, Japan
关键词
Side-channel Attack; Cache Memory; RISC-V; Neutral Network; Hardware Performance Counters;
D O I
10.1109/ISCAS48785.2022.9937212
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The goal of this study is to investigate the problem of caches side-channel attacks on the open-source RISC-V architecture. Traditionally, these concerns have been addressed by research into hardware enhancements or software defense strategies. Those methods are, unfortunately, extremely hard to accomplish or lead to significant performance degradation. In this article, we investigate at a system for identifying cache sidechannel threats such Spectre in real time. We utilize performance counters inside the processor to track the processor's cache behavior and a neural network to evaluate the acquired data. Since the presence of cache side-channels typically results in a dramatically altered cache utilization behaviors, our neural network would take advantage of it and detect a Spectre attack in our test environment with an accuracy of more than 99%. To summarize, we are able to inform the user when a cache side-channel attack occurs using data from only four counters.
引用
收藏
页码:2467 / 2471
页数:5
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