A Parallel 32x32 Time-To-Digital Converter Array Fabricated in a 130 nm Imaging CMOS Technology

被引：0

作者：

Gersbach, M. ^{[1
,5
]}

Maruyama, Y. ^{[5
]}

Labonne, E. ^{[1
]}

Richardson, J. ^{[2
,3
]}

Walker, R. ^{[3
]}

Grant, L. ^{[2
]}

Henderson, R. ^{[3
]}

Borghetti, F. ^{[4
]}

Stoppa, D. ^{[4
]}

Charbon, E. ^{[1
,5
]}

机构：

[1] Ecole Polytech Fed Lausanne, CH-1015 Lausanne, Switzerland

[2] ST Microelectroniocs, Edinburgh, Midlothian, Scotland

[3] Univ Edinburgh, Edinburgh, Midlothian, Scotland

[4] Fondaz Bruno Kessler, Trento, Italy

[5] Delft Univ Technol, Delft, Netherlands

来源：

2009 PROCEEDINGS OF ESSCIRC | 2009年

关键词：

TDC; TDC array; TCSPC; SPAD; FLIM; RESOLUTION; DETECTOR; SENSOR;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We report on the design and characterization of a 32 x 32 time-to-digital converter (TDC) array implemented in a 130 nm imaging CMOS technology. The 10-bit TDCs exhibit a timing resolution of 119 Ps with a timing uniformity across the entire array of less than 2 LSBs. The differential- and integral non-linearity (DNL and INL) were measured at +/- 0.4 and +/- 1.2 LSBs respectively. The TDC array was fabricated with a pitch of 50 mu m in both directions and with a total TDC area of less than 2000 mu m(2). The characteristics of the array make it an excellent candidate for in-pixel TDC in time-resolved imagers for applications such as 3-D imaging and fluorescence lifetime imaging microscopy (FLIM).

引用

页码：197 / +

页数：2

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