Binary Adder Circuit Design Using Emerging MIGFET Devices

被引：0

作者：

Baqueta, Jeferson J. ^{[1
]}

Marranghello, Felipe S. ^{[2
]}

Possani, Vinicius N. ^{[1
]}

Neutzling, Augusto ^{[1
]}

Reis, Andre I. ^{[1
,2
]}

Ribas, Renato P. ^{[1
,2
]}

机构：

[1] Univ Fed Rio Grande do Sul, PPGC, Porto Alegre, RS, Brazil

[2] Univ Fed Rio Grande do Sul, Inst Informat, PGMicro, Porto Alegre, RS, Brazil

来源：

PROCEEDINGS OF THE EIGHTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED) | 2017年

关键词：

Binary adder; emerging technology; MIGFET; digital integrated circuit; ripple-carry adder; parallel-prefix adder; LOGIC GATES; LOW-POWER; FETS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Multiple independent-gate field effect transistors (MIGFETs) have great potential for digital integrated circuits. In this work, we demonstrate that conventional binary adder architectures may benefit from the use of MIGFET devices. As case studies, we have designed ripple-carry adders (RCA) and parallel-prefix adders (PPA), where circuit area and performance optimizations are explored. Different versions of adders have been built using MIGFET and compared to adder topologies based on single-gate transistors.

引用

页码：125 / 130

页数：6

共 50 条

[1] Qualitative Analysis of An Equivalent Full Adder Circuit Using MIGFET An Alternative Approach to Full Adder Circuit via Direct Truth Table Implementation
Karim, Syed Ahsanul
Zaman, Hasan U.
2016 INTERNATIONAL CONFERENCE ON MICROELECTRONICS, COMPUTING AND COMMUNICATIONS (MICROCOM), 2016,
[2] Boolean Circuit Design Using Emerging Tunneling Devices
Sedighi, Behnam
Nahas, Joseph J.
Niemier, Michael
Hu, Xiaobo Sharon
2014 32ND IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), 2014, : 355 - 360
[3] Design of a compact reversible binary coded decimal adder circuit
Babu, HMH
Chowdhury, AR
JOURNAL OF SYSTEMS ARCHITECTURE, 2006, 52 (05) : 272 - 282
[4] DESIGN OF STORING AND RESTORING ARRAY DIVIDER CIRCUIT USING BINARY DECISION DIAGRAM-BASED ADDER/SUBTRACTOR CIRCUIT
Senthilpari, C.
Vishnupriya
Lee, Chu-liang
Deivasigamani, S.
Rosalind
Narmadha, G.
JOURNAL OF ENGINEERING SCIENCE AND TECHNOLOGY, 2024, 19 (04): : 1235 - 1253
[5] DESIGN FOR A PARALLEL BINARY ADDER
EARNSHAW, JB
FENWICK, PM
ELECTRONIC ENGINEERING, 1966, 38 (466): : 794 - &
[6] Dynamic decimal adder circuit design by using the carry lookahead
You, Younggap
Kim, Yong Dae
Choi, Jong Hwa
PROCEEDINGS OF THE 2006 IEEE WORKSHOP ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, 2006, : 244 - +
[7] Design of Full Adder circuit using Double Gate MOSFET
Sahani, Jagdeep Kaur
Singh, Shiwani
2015 5TH INTERNATIONAL CONFERENCE ON ADVANCED COMPUTING & COMMUNICATION TECHNOLOGIES ACCT 2015, 2015, : 57 - 60
[8] Design of Adder and Binary Multiplier in QCA using Coplanar Technique
Kumar, Awanish
Sasamal, Trailokya Nath
PROCEEDINGS OF 2017 INTERNATIONAL CONFERENCE ON INTELLIGENT COMPUTING AND CONTROL (I2C2), 2017,
[9] Circuit design of an adder of small depth
Gashkov S.B.
Grinchuk M.I.
Sergeev I.S.
Journal of Applied and Industrial Mathematics, 2008, 2 (2) : 167 - 178
[10] Memristor Based Adder Circuit Design
Revanna, Nagaraja
Swartzlander, Earl E., Jr.
2016 50TH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS, 2016, : 162 - 166

← 1 2 3 4 5 →