DESIGN OF STORING AND RESTORING ARRAY DIVIDER CIRCUIT USING BINARY DECISION DIAGRAM-BASED ADDER/SUBTRACTOR CIRCUIT

The Binary Decision Diagram (BDD) based circuits are tree-structured, equally sharing the current/power in the cell, which gives reduced power dissipation and increasing speed. The proposed BDD based adder/subtractor circuits are designed and verified in such a way, which trades off the traditional way of full adder/subtractor design, and achieves the required parameters of high speed, low latency, lesser occupying area and low power in the design. The schematic circuits are obtained by using Mentor graphics Silterra 0.13 mu m. The proposed adder/subtractor circuit is implemented into a Restoring Array Divider (RAD) and Non-restoring Array Divider (NRAD) circuits for 5G base station application. The proposed full adder gives a power dissipation (32.11 nW), delay (140 ps) and occupying area (67.5 mu m2), 2 ), which is lower than other reported circuits. The proposed subtractor circuit is compared with the existing circuits, which gives more than 95% improvement in Power dissipation and 17.39% improvement in propagation delay. The layout vs. circuit schematic comparison has been performed for the proposed adder-based RAD and NRAD and evaluated for chip area, propagation delay, and power dissipation. The proposed adder/subtractor-based RAD and NRAD circuits are compared with the results of existing works. The proposed adder/subtractor circuits give 36.02% power dissipation than A, Arya et al. DAXD 99.79% and 99.74% than A. Arya et al. Approximate Divider (ADIV) and Approximate Divider 6 (ADIV6) divider model circuit. The propagation delay and area are improved by 80% in terms of delay and more than 14% in terms of area than the recent report designs.