A hybrid CDAC-threshold configuring SAR ADC in 28nm FDSOI CMOS

被引：0

作者：

Kilic, Mustafa ^{[1
]}

Mavrogordatos, Themistoklis G. ^{[2
]}

Leblebici, Yusuf ^{[1
]}

机构：

[1] Swiss Fed Inst Technol, Microelect Syst Lab, CH-1015 Lausanne, Switzerland

[2] Ctr Suisse Elect & Microtech, Zurich, Switzerland

来源：

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2018年 / 97卷 / 03期

关键词：

SAR ADC; High speed ADC; Threshold configuring; Asynchronous logic; SINGLE-CHANNEL; SPEED; 6-BIT;

D O I：

10.1007/s10470-018-1222-5

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a 9-bit 1.3 GS/s single channel SAR ADC is presented. In conventional SAR ADCs, the capacitive DAC size grows exponentially with respect to converter resolution. This results in both signal bandwidth and conversion speed reduction. The proposed architecture implements binary search through a redundant capacitive DAC for the 5 first MSBs and through programmable comparator thresholds for the remaining 4 LSBs. The DAC capacitance at the front-end remains small enough to achieve high sampling rate with increased input bandwidth. Two asynchronously clocked alternate comparators are used additionally to improve conversion speed. The ADC is designed and simulated in 28 nm FD-SOI CMOS. It consumes 4.1 mW from a 1 V supply, while achieving a SNDR of 52.1 dB and a Figure-of-Merit of 11.4 fJ/conversion-step.

引用

页码：397 / 404

页数：8

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