Analysis of thin gate oxide degradation during fabrication of advanced CMOS ULSI circuits

被引:10
|
作者
Kim, SU [1 ]
机构
[1] SEMATECH, Strateg Technol, Austin, TX 78741 USA
关键词
Number:; -; Acronym:; TEM; Sponsor: Työ- ja Elinkeinoministeriö;
D O I
10.1109/16.661235
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The electrical characteristics uniquely associated with the thin gate oxide degradation of the advanced CMOS technology in manufacturing were determined for the first time. They were different from Fowler-Nordheim (F-N) stress, and therefore, cannot be simulated by the F-N stress, The p(+) thin gate oxides were found to be inherently more susceptible to gate oxide degradation than the n(+) gate oxides. The p(+) oxide degradation is caused by a combination of the process-induced defect and plasma charging, The nature of the defect and its formation were identified by electrical and physical analysis. The defect formation was modeled. The p-channel gate oxide degradation will be worse with gate oxide scaling, and may limit the device scaling.
引用
收藏
页码:731 / 736
页数:6
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