FPGA based design and prototyping of efficient 5G QC-LDPC channel decoding

The Quasi-Cyclic (QC) Low-Density ParityCode (LDPC) is the key error correction code for the 5th Generation (5G) of cellular network technology. Designed to support several frame sizes and code rates, the 5G LDPC code structure allows high parallelism to deliver the high demanding data rate of 10 Gb/s. This impressive performance introduces challenging constraints on the hardware design. Particularly, allowing such high flexibility can introduce processing rate penalties on some configurations. In this context, a novel efficient and flexible hardware architecture for the 5G LDPC decoder is proposed, targeting Field Programmable Gate Array (FPGA) devices and supporting all 5G configurations. The architecture supports frame parallelism to maximize the utilization of the processing units, significantly improving the processing rate. Compared to a recent commercial 5G LDPC decoder, the proposed FPGA prototype achieves a higher processing rate for most configurations while having similar complexity.