Power and thermal modeling approach for homogeneously stacked butterfly fat tree architecture in 3D ICs

Low-power consumption and heat dissipation are becoming serious issues in the design process of the 3D integrated circuit (IC). The multiple dies are stacked and communicated through-silicon vias to work as a single device to achieve high performance with minimum power and heat dissipation. This paper presents the power and thermal modeling approaches for the power/heat estimation of homogenous integration of network-on-chip-based tree architecture in 3D IC design. The preliminary experimental work of power model is divided in 2 major parts of the design. The first part estimates the power of network-on-chip tree architecture on each stack/layer separately, and the second estimates the power dissipation of the uniformly distributed through-silicon vias and input/output pads. The model uses a linear function to estimate the average power dissipation. The thermal model estimates the heat dissipation by using thermal sensors on different sections of the individual layer. For an entire IC design, the average power/thermal is extracted by simple addition of all power/thermal estimation results of the model. The design is operated with multiple frequencies to find the most appropriate frequency to minimize power dissipation. In experiments, the average maximum error is estimated 16.29%.