共 50 条
- [1] A Cu interconnect process for the 130nm process technology node [J]. ADVANCED METALLIZATION CONFERENCE 2001 (AMC 2001), 2001, : 39 - 41
- [2] TCAD simulation of STI stress effect on active length for 130nm technology [J]. 2006 IEEE INTERNATIONAL CONFERENCE ON SEMICONDUCTOR ELECTRONICS, PROCEEDINGS, 2006, : 1038 - +
- [3] Optimization for full chip process of 130nm technology with 248nm DUV lithography [J]. OPTICAL MICROLITHOGRAPHY XIII, PTS 1 AND 2, 2000, 4000 : 1053 - 1061
- [5] Laser Study for DICE-based Registers in a Commercial 130nm Process Technology [J]. 2019 IEEE 4TH INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUITS AND MICROSYSTEMS (ICICM 2019), 2019, : 170 - 173
- [6] Implementation of Linear Discriminant Classifier in 130nm Silicon Process [J]. 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2018,
- [7] Study of reticle cleaning process for 130nm lithography and beyond [J]. PHOTOMASK AND NEXT-GENERATION LITHOGRAPHY MASK TECHNOLOGY VIII, 2001, 4409 : 430 - 437
- [8] Challenges in detecting and analyzing process-induced damage for 130nm CMOS technology and beyond [J]. 2002 7TH INTERNATIONAL SYMPOSIUM ON PLASMA- AND PROCESS-INDUCED DAMAGE, 2002, : 31 - 36
- [9] Lithography process optimization for 130nm poly gate mask and the impact of mask error factor [J]. METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XV, 2001, 4344 : 783 - 796
- [10] A Single Photon Detector Implemented in a 130nm CMOS Imaging Process [J]. ESSDERC 2008: PROCEEDINGS OF THE 38TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2008, : 270 - +