GALS Test Chip on 130nm Process

被引：3

作者：

Bormann, David S. ^{[1
]}

机构：

[1] Intel Corp, Intel Labs, Santa Clara, CA 95054 USA

来源：

ELECTRONIC NOTES IN THEORETICAL COMPUTER SCIENCE | 2006年 / 146卷 / 02期

关键词：

GALS; asynchronous wrapper; local clock; stretchable clock; AFSM;

D O I：

10.1016/j.entcs.2005.05.034

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

We present a Globally Asynchronous Locally Synchronous test chip fabricated on a 130nm silicon process. The primary design goals of this chip were to measure the stability of local clocks on a deep submicron process technology, evaluate difficulties using GALS in a standard design flow, and to measure power consumption. The original Asynchronous Wrapper building blocks were used to construct a configurable data pipeline that can be tuned to emulate the operation of many different types of algorithms.

引用

页码：29 / 40

页数：12

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