Floorplanning for 3D-IC with Through-Silicon Via Co-Design Using Simulated Annealing

In this paper, we will propose a method for floorplanning in three dimensional integrated circuits (3D-IC), considering the impact of Through-Silicon-Via (TSV). In 3D-IC, multiple device layers are vertically stacked and interconnected by excessive amount of TSVs which occupy a lot of silicon area and increase wire length. In this paper, a simulated annealing (SA) multi-objective optimization algorithm is developed for 3D-IC including the factors of floorplanning, plan functional block and TSV simultaneously. By using this SA method, we can get a floorplanning with minimum TSVs, thus reduces the silicon area and wire length.