Thermal Budget Reduction in Triple Gate Oxide Process by Wet Etch Technique

As transistor geometry shrink and System on Chip (SoC) requirements increase, chips with multiple operation voltages become regular criteria in IC design specification. This means that multiple gate oxide thicknesses have to be integrated in semiconductor manufacturing front-end-of-line (FEOL) process. However, process thermal budget will be one of the concerns of transistor electrical performance shift resulted from diffusion of implantation species. In this study, thicker gate oxide (MV) was etched back by wet chemical as thinner gate oxide (I/O) to reduce gate oxide formation thermal budget. However, wet etching rate was degraded after clean and lithograph sequential processes. The oxidant, in wet clean chemical, oxidized silicon dioxide surface SiH bonding into Si-OH which reacted with Hexamethyldisilazane (HMDS), commonly used as lithography adhesion material, and form an extremely thin Trimethylsiloxy monolayer (Si-O-Si(CH3)(3)) on the gate oxide surface. Fortunately, Trimethylsiloxy monolayer consists of Si-O bonding and Trimethylsilyl group (-Si(CH3)(3)) and can be easily removed by O-2 plasma treatment.