Combinational verification based on high-level functional specifications

被引:1
|
作者
Goldberg, EI [1 ]
Kukimoto, Y [1 ]
Brayton, RK [1 ]
机构
[1] Cadence Berkeley Labs, Berkeley, CA 94704 USA
关键词
D O I
10.1109/DATE.1998.655950
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We present a new combinational verification technique where the functional specification of a circuit under verification is utilized to simplify the verification task. The main idea is to assign to each primary input a general function, called a coordinate function, instead of a single variable function as in most BDD-based techniques. BDDs of intermediate nodes are then constructed based on these coordinate functions in a topological order from primary inputs to primary outputs. Coordinate functions depend on primary input variables and extra variables. Therefore combinational verification is performed not over the set of primary input variables but over the extended set of variables. Coordinate functions are chosen in such a way that in the process of computing intermediate functions the dependency on the primary input variables is gradually replaced with that on the extra variables, thereby making boolean functions associated with primary outputs simple functions only in terms of the extra variables. We show that such a smart choice of coordinate functions is possible with the help of the high level functional specification of the circuit.
引用
收藏
页码:803 / 808
页数:6
相关论文
共 50 条
  • [41] Towards high-level, verifiable autonomous behaviors with temporal specifications
    Wang, Ju
    Pandit, Sagar
    PROCEEDINGS OF THE 2019 IEEE NATIONAL AEROSPACE AND ELECTRONICS CONFERENCE (NAECON), 2019, : 92 - 99
  • [43] Minimizing the Information Leakage Regarding High-Level Task Specifications
    Hibbard, Michael
    Savas, Yagiz
    Xu, Zhe
    Topcu, Ufuk
    IFAC PAPERSONLINE, 2020, 53 (02): : 15388 - 15395
  • [44] Simulation and validation of high-level abstract state machine specifications
    Del Castillo, G
    Glässer, U
    ESM'99 - MODELLING AND SIMULATION: A TOOL FOR THE NEXT MILLENNIUM, VOL II, 1999, : 463 - 465
  • [45] Automated generation of marshaling code from high-level specifications
    Weigert, T
    Dietz, P
    SDL 2003: SYSTEM DESIGN, PROCEEDINGS, 2003, 2708 : 374 - 386
  • [46] HIGH-LEVEL TIMED PETRI NETS AS A KERNEL FOR EXECUTABLE SPECIFICATIONS
    FELDER, M
    GHEZZI, C
    PEZZE, M
    REAL-TIME SYSTEMS, 1993, 5 (2-3) : 235 - 248
  • [47] Validating Traces of Distributed Programs against High-Level Specifications
    Merz, Stephan
    ELECTRONIC PROCEEDINGS IN THEORETICAL COMPUTER SCIENCE, 2024, (399): : 3 - 3
  • [48] Rapid estimation of control delay from high-level specifications
    Gupta, Gagan Raj
    Gupta, Madhur
    Panda, Preeti Ranjan
    43RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2006, 2006, : 455 - +
  • [49] A methodology to take credit for high-level verification during RTL verification
    Frederic Doucet
    Robert Kurshan
    Formal Methods in System Design, 2017, 51 : 395 - 418
  • [50] A methodology to take credit for high-level verification during RTL verification
    Doucet, Frederic
    Kurshan, Robert
    FORMAL METHODS IN SYSTEM DESIGN, 2017, 51 (02) : 395 - 418