Device design methodology and reliability strategy for deep sub-micron technology

被引：0
|
作者：
Divakaruni, R [1 ]
El-Kareh, B [1 ]
Tonti, WR [1 ]
机构：
[1] IBM Microelect, Essex Junction, VT USA
来源：
1997 IEEE INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP FINAL REPORT | 1997年
关键词：
D O I：
10.1109/IRWS.1997.660315
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
This tutorial will discuss device and process optimization techniques that may be employed in the design of present state of the art bulk silicon DRAM technology. MOSFET performance and reliability issues are contrasted.
引用
收藏
页码：147 / 152
页数：6
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