共 50 条
- [22] Modeling and characterization of Cu wire bonding process on silicon chip with 45nm node and Cu/low-k structures PROCEEDINGS OF THE 2013 IEEE 15TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC 2013), 2013, : 270 - 275
- [23] Characteristic of heat affected zone in thin gold wire and dynamic transient analysis of wire bonding for microstructure of Cu/Low-K wafer 2007 INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY AND CIRCUITS TECHNOLOGY CONFERENCE, PROCEEDINGS OF TECHNICAL PAPERS, 2007, : 297 - +
- [24] Impact of packaging materials on reliability test for low-K wire bond-stacked flip chip CSP Journal of Materials Science: Materials in Electronics, 2009, 20 : 484 - 489
- [26] Computational Modeling and Optimization for Wire Bonding Process on Cu/Low-K Wafers 2009 INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY & HIGH DENSITY PACKAGING (ICEPT-HDP 2009), 2009, : 268 - 276
- [27] Numerical study of gold wire bonding process on Cu/Low-k structures IEEE TRANSACTIONS ON ADVANCED PACKAGING, 2007, 30 (03): : 448 - 456
- [28] A reliable wire bonding on 130nm Cu/low-k device PROCEEDINGS OF 5TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, 2003, : 707 - 711
- [29] Stress Analysis and Design Optimization for Low-k Chip With Cu Pillar Interconnection IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2015, 5 (09): : 1273 - 1283
- [30] Dynamic finite element analysis on underlay microstructure of Cu/low-K wafer during bonding process 2007 INTERNATIONAL CONFERENCE ON ELECTRONIC MATERIALS AND PACKAGING, 2007, : 383 - +