High performance Viterbi decoder design

被引:0
|
作者
Kavitha, V. [1 ]
Mohanraj, S. [1 ]
机构
[1] M Kumarasamy Coll Engn, Dept Elect & Commun Engn, Karur, Tamil Nadu, India
关键词
Viterbi decoder; SMU algorithm; Register exchange architecture;
D O I
10.1007/s10586-018-2295-8
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Viterbi decoder may be a regular module over correspondence framework in which energy also deciphering inactivity need aid demand. Register Exchange (RE) building design need the most reduced deciphering inactivity l. However, it is not suitable for correspondence framework due to its secondary force utilization. In this paper, it is recommended another SMU structural engineering which combines the idea of the trace-forward and also trace-back. Those deciphering inactivity of the suggested SMU calculation may be main L+M. Besides, we display a force productive building design for the recommended SMU algorithm. The recommended structural engineering is executed in Xilinx ISE 12. 3 for focus gadget may be Vertex6 FPGA. The control utilization of the suggested construction modeling is marginally higher over those 3-pointer.
引用
收藏
页码:S7063 / S7068
页数:6
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