Prototyping of a high performance generic Viterbi decoder

被引：3

作者：

Obeid, AM ^{[1
]}

Ortiz, AG ^{[1
]}

Ludewig, R ^{[1
]}

Glesner, M ^{[1
]}

机构：

[1] TH Darmstadt, Inst Microelect Syst, D-64283 Darmstadt, Germany

来源：

13TH IEEE INTERNATIONAL WORKSHOP ON RAPID SYSTEM PROTOTYPING, PROCEEDINGS | 2002年

关键词：

D O I：

10.1109/IWRSP.2002.1029736

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

For its proven efficiency, the Viterbi algorithm is widely used for decoding convolutionally encoded messages. In this work, a high performance generic soft input hard output Viterbi decoder is presented and prototyped on an FPGA board. The presented Viterbi decoder is intended to be used in a complete wireless LAN transceiver prototype. The genericity of the design facilitates not only the prototyping of Viterbi decoders with different specifications, but moreover it facilitates the exploration the performance of different implementations in order to obtain the most suitable solution for a particular communication system.

引用

页码：42 / 47

页数：6

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