A 6-bit 1 GHz acquisition speed CMOS flash ADC with digital error correction

被引：29
|
作者：
Uyttenhove, K [1 ]
Marques, A [1 ]
Steyaert, M [1 ]
机构：
[1] Katholieke Univ Leuven, Dept Elektrotech, Afd ESAT, MICAS, B-3001 Heverlee, Belgium
来源：
PROCEEDINGS OF THE IEEE 2000 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2000年
关键词：
D O I：
10.1109/CICC.2000.852659
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, a 6-bit CMOS analog-to-digital converter (A/D) with a maximum acquisition speed of 1 GHz is presented. The problem of meta-stability has got special attention in this design, since this problem degrades the Spurious-Free Dynamic Range (SFDR) at high sampling frequencies. Measured SNDR (Signal to noise plus distortion) is over 30 dB at 500MHz clock and f(IN) = 141 kHz. The measured SFDR for input frequencies up to 250 MHz is over 30dB. The chip has been processed in a standard 0.35 mu m CMOS technology with double poly and occupies an active area of 0.8 mm(2).
引用
收藏
页码：249 / 252
页数：4
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