Low power multiplier with bypassing and tree strucuture

被引：0

作者：

Kuo, Ko-Chi ^{[1
]}

Chou, Chi-Wen ^{[1
]}

机构：

[1] Natl Sun Yat Sen Univ, Dept Comp Sci & Engn, Kaohsiung 80424, Taiwan

来源：

2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS | 2006年

关键词：

multiplier; bypassing method; tree structure; low power;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a new design technique for low power multiplier is introduced. This technique utilizes the bypassing method to minimize the switching activities and tree structure decrease the critical path. The design of circuit uses the standard TSMC 0.18 mu m technology. According to the simulation results, the proposed multiplier design can obtain more power savings than those of counterparts and achieve smaller power-delay product.

引用

页码：602 / +

页数：2

共 50 条

[41] Low-Power Modified Vedic Multiplier
Kodali, Ravi Kishore
Sivakumar, C.
Jain, Vishal
Boppana, Lakshmi
2015 INTERNATIONAL CONFERENCE ON CONTROL COMMUNICATION & COMPUTING INDIA (ICCC), 2015, : 454 - 458
[42] A low-power multiplier with the spurious power suppression technique
Chen, Kuan-Hung
Chu, Yuan-Sun
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2007, 15 (07) : 846 - 850
[43] Multiplier energy reduction through bypassing of partial products
Ohban, J
Moshnyaga, VG
Inoue, K
APCCAS 2002: ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS, 2002, : 13 - 17
[44] DATA BYPASSING REGISTER FILE FOR LOW-POWER MICROPROCESSOR
IKEDA, M
ASADA, K
IEICE TRANSACTIONS ON ELECTRONICS, 1995, E78C (10) : 1470 - 1472
[45] Design of Area and Power Aware Reduced Complexity Wallace Tree Multiplier
Kakde, Sandeep
Khan, Shahebaj
Dakhole, Pravin
Badwaik, Shailendra
2015 INTERNATIONAL CONFERENCE ON PERVASIVE COMPUTING (ICPC), 2015,
[46] A power-aware 2-dimensional bypassing multiplier using cell-based design flow
Sung, Gang-Neng
Ciou, Yan-Jhih
Wang, Chua-Chin
PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 2008, : 3338 - 3341
[47] Design of Low-Power Square Root Carry Select Adder and Wallace Tree Multiplier Using Adiabatic Logic
Ganavi, M. G.
Premananda, B. S.
EMERGING RESEARCH IN ELECTRONICS, COMPUTER SCIENCE AND TECHNOLOGY, ICERECT 2018, 2019, 545 : 767 - 781
[48] Design of Low Power Reconfigurable Floating Point Multiplier
Pandey, Deepak
Sharma, R. K.
2016 CONFERENCE ON ADVANCES IN SIGNAL PROCESSING (CASP), 2016, : 276 - 279
[49] Low power design techniques for a Montgomery modular multiplier
Wang, X
Noel, P
Kwasniewski, T
ISPACS 2005: PROCEEDINGS OF THE 2005 INTERNATIONAL SYMPOSIUM ON INTELLIGENT SIGNAL PROCESSING AND COMMUNICATION SYSTEMS, 2005, : 449 - 452
[50] Switching activity reduction in low power booth multiplier
Mudassir, Rizwan
Anis, Mohab
Jaffari, Javid
PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 2008, : 3306 - 3309

← 1 2 3 4 5 →