Recent advances in wire bonding, flip chip and lead-free solder for advanced microelectronics packaging

被引：27
|
作者：
Zhong, Z. W. [1 ]
Tee, T. Y.
Luan, J-E.
机构：
[1] Nanyang Technol Univ, Sch MAE, Singapore, Singapore
[2] Amkor Technol Singapore, Singapore, Singapore
[3] STMicroelect, Singapore, Singapore
来源：
MICROELECTRONICS INTERNATIONAL | 2007年 / 24卷 / 03期
关键词：
wires; joining process; soldering; JOINT RELIABILITY-ANALYSIS; NM TECHNOLOGY NODE; THERMOMECHANICAL RELIABILITY; ELECTRONIC PACKAGES; FAILURE ANALYSIS; MOIRE TECHNIQUE; SILICON-WAFERS; PITCH; CHALLENGES; SUBSTRATE;
D O I：
10.1108/13565360710779154
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Purpose - This paper seeks to review recent advances in wire bonding, flip chip and lead-free solder for advanced microelectronics packaging. Design/methodology/approach - Of the 91 journal papers, 59 were published in 2005-2007 and topics related to wire bonding, flip chip and lead-free solder for. advanced microelectronics packaging are reviewed. Findings - Research on advanced wire bonding is continuously performed for advanced and complex applications such as stacked-dies wire bonding, wire bonding of low-k ultra-fine-pitch devices, and copper wire bonding. Owing to its many advantages, flip chip using adhesive has gained more popularity. Research on the reliability of lead-free solder joints is being conducted world-wide. The new challenges, solutions and new developments are discussed in this paper. Research limitations/implications - Because of page limitation of this review paper and the large number of the journal papers available, only a brief review is conducted. Further reading is needed for more details. Originality/value - This review paper attempts to provide introduction to recent developments and the trends in terms of the topics for advanced microelectronics packaging. With the references provided, readers may explore more deeply, focusing on a particular issue.
引用
收藏
页码：18 / 26
页数：9
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