Balancing of Peak Currents between Paralleled SiC MOSFETs by Source Impedances

The peak switching currents of two paralleled MOSFETs turned on/off by one gate driver could differ significantly owing to the mismatch in threshold voltages (V-th). The passive balancing method described herein employs one inductor and one resistor per MOSFET to force the currents to track with negligible penalty in loss. Sensors, feedbacks, and knowledge of gate-related parameters (like gate charge, polarity of V-th difference, gate impedances, etc.) are not required. The passive components are designed using an inequality involving V-th, rise time, and unbalance percentage. The mismatch in peak currents is reduced from 15% to 1% between SiC MOSFETs tested at 20 A and 300 V with 19% V-th variation.