An architecture of a high-speed digital hologram generator based on FPGA

In this paper, a hardware architecture to generate a computer-generated hologram (CGH) in a real-time is proposed and implemented in FPGAs. The algorithm that generates digital hologram is reinterpreted and rearranged for higher operation speed. In order to optimize the hardware architecture and performance, the precision is analyzed using fixed-point simulation. The bit-width inside the hardware is obtained by numerical and visual precision analysis. The structure of the basic calculational unit (CGH Cell), an arrangement of these cells (CGH Kernel) to calculate a row of a hologram, and a processor (CGH Processor) with the kernels to perform the modified CGH algorithm are proposed. The proposed processor was implemented with Xilinx XC2VP70 FPGAs. A 1408 x 1050 sized hologram for a 3D object consisting of 10,000 light sources can be generated in 0.0093 [s] at the operating frequency of 285 MHz. Our architecture showed 37.32% and 87.32% higher speed than the best previous work when 1408 cells and 5632 cells are used, respectively. (C) 2009 Elsevier B.V. All rights reserved.