Effect of Metal Gate Granularity Induced Random Fluctuations on Si Gate-All-Around Nanowire MOSFET 6-T SRAM Cell Stability

In this paper, we present a variability-aware 3-D mixed-mode device simulation study of Si gate-all-around (GAA) nanowire MOSFET (NWFET)-based 6-T static random access memory (SRAM) bit-cell stability and performance considering metal-gate granularity (MGG) induced intrinsic device random fluctuations and quantum corrected room temperature drift-diffusion transport. The impact of MGG contributed intrinsic variability on Si GAA n-and p-NWFETs-based SRAM cell static noise margins (SNM), write and read delay time are statistically analyzed. Our statistical simulations predict acceptable stability for the Si NWFET 6-T SRAM cell with V-DD downscaling up to 0.5 V. The simulation estimated mean hold SNM values follow a lowering trend with V-DD downscaling, similar to the hold SNM experimental data reported in the literature for Si GAA NWFET-based SRAM arrays. We further show a linear variation in statistical variance of hold SNM with gate metal grain size and work function.