Metal-Gate Granularity-Induced Threshold Voltage Variability and Mismatch in Si Gate-All-Around Nanowire n-MOSFETs

被引：32

作者：

Nayak, Kaushik ^{[1
]}

Agarwal, Samarth ^{[2
]}

Bajaj, Mohit ^{[2
]}

Oldiges, Philip J. ^{[3
]}

Murali, Kota V. R. M. ^{[2
]}

Rao, Valipe Ramgopal ^{[1
]}

机构：

[1] IIT, Ctr Excellence Nanoelect, Dept Elect Engn, Bombay 400076, Maharashtra, India

[2] IBM India, Semicond Res & Dev Ctr, Bangalore 560045, Karnataka, India

[3] IBM Corp, Semicond Res & Dev Ctr, Hopewell Jct, NY 12533 USA

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2014年 / 61卷 / 11期

关键词：

Gate-all-around (GAA); metal-gate granularity (MGG); mismatch; silicon nanowire FET; threshold voltage; variability; work function (WF); WORK FUNCTION; PERFORMANCE; DEVICE;

D O I：

10.1109/TED.2014.2351401

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The metal-gate granularity-induced threshold voltage (V-T) variability and V-T mismatch in Si gate-all-around (GAA) nanowire n-MOSFETs (n-NWFETs) are studied using coupled 3-D statistical device simulations considering quantum corrected room temperature drift-diffusion transport. The impact of metal-gate crystal grain size on linear and saturation mode V-T variability are analyzed. The V-T mismatch study predicts lower mismatch figure of merit (A(VT)) in TiN-gated Si GAA n-NWFETs compared with the reported experimental mismatch data for TiN-gated Si FinFETs.

引用

页码：3892 / 3895

页数：4

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