Failure analysis of 6T SRAM on low-voltage and high-frequency operation

被引：18

作者：

Ikeda, S ^{[1
]}

Yoshida, Y

Ishibashi, K

Mitsui, Y

机构：

[1] Trecenti Technol Inc, Ibaraki 3120034, Japan

[2] Hitachi High Technol Inc, Ibaraki, Japan

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2003年 / 50卷 / 05期

关键词：

grain size (new); high-speed integrated circuits; hydrazine (new); low voltage (new); nanoprobe (new); noise; SRAM chips; stability;

D O I：

10.1109/TED.2003.813474

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Careful analysis of SRAM bit failure at high-frequency operation has been described. Using the nanoprober technique, MOS characteristics of failure bit in actual memory cells had been measured directly. It was confirmed that the drain current of a PMOS was about one order in magnitude smaller and the threshold voltage was about 1 V higher than that for normal bits.. A newly developed, unique selective etching technique using hydrazine mixture showed these degradations were caused by local gate depletion, and TEM observation showed the PMOS gate poly-Si of the failure bit had a huge grain. Minimizing grain size of the gate poly-Si is found to be quite effective for improving drain current degradation and suppressing this failure mode.

引用

页码：1270 / 1276

页数：7

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