Design and realization of high performance CMOS compatible Lateral Bipolar Transistors (CLBTs)

被引：0
|
作者：
Kumar, NR
Sankar, GK
Roy, JN
Singh, DN
机构：
来源：
PROCEEDING OF THE TENTH INTERNATIONAL WORKSHOP ON THE PHYSICS OF SEMICONDUCTOR DEVICES, VOLS I AND II | 2000年 / 3975卷
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中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
Layout techniques to improve the performance of CMOS compatible Lateral Bipolar Transistors (CLBTs) are presented The current ratio of active collector (C-1) and the unwanted substrate collector (C-2) is taken as the figure of merit for these devices. The devices with different emitter geometry were realized in a standard 0.8 mu m 5 V N-Well based twin-tub bulk CMOS process developed at authors' organization A significant improvement was observed in the performance of lateral bipolar action by increasing the emitter periphery to area ratio. The electrical characteristics of the device were analyzed and presented.
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页码：430 / 433
页数：4
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