Low-Power Logic Design Based on Gate Driving Way Considering Interconnections Capacitances

This paper presents design method of low-power integrated circuits based on information on primary inputs vectors changes, considering interconnections in real chip. The tested chip, which includes 32 digital circuits, was designed in CMOS AMS 0.35 mu m technology. Taking advantage of gate driving way - the reason of a gate switching - two-level logic functions were synthesized for low-power. Previously developed design methods: proper choosing of a function cover, and 2-level circuit transformation into 3-level, have been modified. So now interconnection capacitance is evaluated and taken into consideration during logic synthesis. Additionally some post layout simulations were done for verification.