Fully utilized and low memory-bandwidth architecture design of variable block-size motion estimation for H.264/AVC

被引：0

作者：

Chen, Liang-Bin ^{[1
]}

Zhang, Yi-Zhen ^{[1
]}

Xu, Chao ^{[1
]}

机构：

[1] Peking Univ, Natl Lab Machine Percept, No 5,Yiheyuan Rd, Beijing 100871, Peoples R China

来源：

TENCON 2006 - 2006 IEEE REGION 10 CONFERENCE, VOLS 1-4 | 2006年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

In this paper, we present a novel VLSI architecture for Variable Block Size Motion Estimation (VBSME) which not only enhances the PE utilization to 100% but also reduces the memory bandwidth to 1%similar to 25% of the former designs with the same chip size. Based on a 16 X 31 Search Area Register Array (SARA) to buffer 16 rows of Search Area so as to increase the data reusability and two 16X 16 Current Block Register Arrays (CBRA) for ping-pong mode, the design allows serial data input and parallel data processing. At the same time, it solves the problem of current block switch in all conditions. Our design was implemented by Synopsys Design Compiler with SMIC 0.18 cell library. Under a clock frequency of 200MHz, the architecture allows real-time processing of D1 (720 X 480) @ 30fps in a search range of [-32,+31] horizontally and vertically with 123.1k gates.

引用

页码：1028 / +

页数：2

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