System-in-Package, a combination of challenges and solutions

被引：0
|
作者：
Cauvet, P. [1 ]
Bernard, S. [2 ]
Renove, M. [2 ]
机构：
[1] NXP Semicond, 2 Esplanade Anton Philips,BP20000, F-14906 Caen 9, France
[2] Univ Montpellier, LIRMM, F-34392 Montpellier, France
来源：
ETS 2007: 12TH IEEE EUROPEAN TEST SYMPOSIUM, PROCEEDINGS | 2007年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
System-in-Package (SiP) has recently become a significant technology in the semiconductor industry, offering to the consumer applications many new product features without increasing the overall form factor. In this talk, the basic SiP concepts are first discussed, showing difference between SiP and SoC, illustrated by some examples, drawn from real-life cases. The specific challenges are considered from the testing point of view, focussing on the assembled yield and defect level for the packaged SiP. Various bare-die test techniques to find known-good-dies are described including their limitations, followed by two techniques to test the SiP at the system level: functional system test and embedded component test. A brief discussion on future SiP design and test challenges concludes the presentation.
引用
收藏
页码：193 / +
页数：3
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