System-in-Package, a combination of challenges and solutions

被引：0
|
作者：
Cauvet, P. [1 ]
Bernard, S. [2 ]
Renove, M. [2 ]
机构：
[1] NXP Semicond, 2 Esplanade Anton Philips,BP20000, F-14906 Caen 9, France
[2] Univ Montpellier, LIRMM, F-34392 Montpellier, France
来源：
ETS 2007: 12TH IEEE EUROPEAN TEST SYMPOSIUM, PROCEEDINGS | 2007年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
System-in-Package (SiP) has recently become a significant technology in the semiconductor industry, offering to the consumer applications many new product features without increasing the overall form factor. In this talk, the basic SiP concepts are first discussed, showing difference between SiP and SoC, illustrated by some examples, drawn from real-life cases. The specific challenges are considered from the testing point of view, focussing on the assembled yield and defect level for the packaged SiP. Various bare-die test techniques to find known-good-dies are described including their limitations, followed by two techniques to test the SiP at the system level: functional system test and embedded component test. A brief discussion on future SiP design and test challenges concludes the presentation.
引用
收藏
页码：193 / +
页数：3
相关论文
共 50 条
  • [1] System-in-package technology: Opportunities and challenges
    Fontanelli, Anna
    ISQED 2008: PROCEEDINGS OF THE NINTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2008, : 589 - 593
  • [2] System-in-package testing: Problems and solutions
    Appello, Davide
    Bernardi, Paolo
    Grosso, Michelangelo
    Reorda, Matteo Sonza
    IEEE DESIGN & TEST OF COMPUTERS, 2006, 23 (03): : 203 - 211
  • [3] Broadening the platforms for system-in-package solutions
    Truzzi, C
    Lerner, S
    SOLID STATE TECHNOLOGY, 2000, 43 (11) : 115 - +
  • [4] Challenges and opportunities in System-in-Package (SiP) business
    Sham, M. L.
    Chen, Y. C.
    Leung, T. W.
    Lin, J. R.
    Chung, T.
    ICEPT: 2006 7TH INTERNATIONAL CONFERENCE ON ELECTRONICS PACKAGING TECHNOLOGY, PROCEEDINGS, 2006, : 26 - +
  • [5] Packaging technology trends and challenges for system-in-package
    Dohya, A
    IEICE TRANSACTIONS ON ELECTRONICS, 2001, E84C (12) : 1756 - 1762
  • [6] Design challenges for System-In-Package vs System-On-Chip
    Trigas, C
    PROCEEDINGS OF THE IEEE 2003 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2003, : 663 - 666
  • [7] Interconnection modeling challenges in system-in-package (SiP) design
    Castorina, S.
    Ene, R. A.
    SCIENTIFIC COMPUTING IN ELECTRICAL ENGINEERING, 2006, 9 : 413 - +
  • [8] System-in-Package (SiP) design: Issues, approaches and solutions
    Leung, L. L. W.
    Sham, M. L.
    Ma, W.
    Chen, Y. C.
    Lin, J. R.
    Chung, T.
    2006 INTERNATIONAL CONFERENCE ON ELECTRONIC MATERIALS AND PACKAGING, VOLS 1-3, 2006, : 772 - 776
  • [9] European Project on Integrated Electronic System-in-Package Solutions
    Mumford, Richard
    MICROWAVE JOURNAL, 2010, 53 (09) : 53 - 54
  • [10] Substrate transfer: An enabling technology for system-in-package solutions
    Dekker, R.
    Duemling, M.
    Fock, J. -H.
    Haartsen, J. R.
    Maas, H. G. R.
    Michielsen, T. M.
    Pohlmann, H.
    Schnitt, W.
    Tombeur, A. M. H.
    PROCEEDINGS OF THE 2006 BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING, 2006, : 178 - +
12345