Low-complexity bit-parallel systolic multipliers over GF(2m)

被引：3
|
作者：
Chiou-Yng Lee
Chin-Chin Chen
Yuan-Ho Chen
Erl-Huei Lu
机构：
来源：
2006 IEEE INTERNATIONAL CONFERENCE ON SYSTEMS, MAN, AND CYBERNETICS, VOLS 1-6, PROCEEDINGS | 2006年
关键词：
systolic array; folded technique; primitive polynomial; interleaved conventional multiplication;
D O I：
10.1109/ICSMC.2006.384557
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
Recently, cryptographic applications based on finite fields have attracted much interest. This paper presents two new algorithms, called time-dependent and time-independent multiplication algorithms over a finite field GF(2(m)) by employing an interleaved conventional multiplication and a folded technique. The proposed algorithms permit efficient realization of the bit-parallel multiplication using iterative arrays. The results show that our proposed time-dependent and time-independent multipliers save about 38% and 54% space complexity as compared to the traditional multipliers, respectively.
引用
收藏
页码：1160 / 1165
页数：6
相关论文
共 50 条
  • [1] Low-complexity bit-parallel systolic multipliers over GF(2m)
    Lee, Chiou-Yng
    INTEGRATION-THE VLSI JOURNAL, 2008, 41 (01) : 106 - 112
  • [2] Low-complexity bit-parallel systolic Montgomery multipliers for special classes of GF(2m)
    Lee, CY
    Horng, JS
    Jou, IC
    Lu, EH
    IEEE TRANSACTIONS ON COMPUTERS, 2005, 54 (09) : 1061 - 1070
  • [3] Multiplexer-based bit-parallel systolic multipliers over GF(2m)
    Lee, Chiou-Yng
    COMPUTERS & ELECTRICAL ENGINEERING, 2008, 34 (05) : 392 - 405
  • [4] Ringed bit-parallel systolic multipliers over a class of fields GF(2m)
    Ting, YR
    Lu, EH
    Lu, YC
    INTEGRATION-THE VLSI JOURNAL, 2005, 38 (04) : 571 - 578
  • [5] Bit-parallel systolic modular multipliers for a class of GF(2m)
    Lee, CY
    Lu, EH
    Lee, JY
    ARITH-15 2001: 15TH SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 2001, : 51 - 58
  • [6] The design of a low-complexity systolic architecture for fast bit-parallel exponentiation in a class of GF(2m)
    Lee, CY
    Lu, EH
    Sun, LF
    2000 5TH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING PROCEEDINGS, VOLS I-III, 2000, : 598 - 605
  • [7] Low-complexity bit-parallel systolic architectures for computing A(x)B2(x) over GF(2m)
    Lee, C. -Y.
    Chiou, C. W.
    Deng, A. -W.
    Lin, J. -M
    IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 2006, 153 (04): : 399 - 406
  • [8] Efficient design of low-complexity bit-parallel systolic hankel multipliers to implement multiplication in normal and dual bases of GF (2m)
    Lee, CY
    Chiou, CW
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2005, E88A (11): : 3169 - 3179
  • [9] Low complexity bit-parallel systolic multiplier over GF(2m) using irreducible trinomials
    Lee, CY
    IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, 2003, 150 (01): : 39 - 42
  • [10] Low-complexity design of bit-parallel dual-basis multiplier over GF(2m)
    Wang, J. -H.
    Chang, H. W.
    Chiou, C. W.
    Liang, W. -Y.
    IET INFORMATION SECURITY, 2012, 6 (04) : 324 - 328
12345