Reducing memory accesses with a system-level design methodology in customized dynamic memory management

被引:0
|
作者
Atienza, D [1 ]
Mamagkakis, S [1 ]
Catthoor, F [1 ]
Mendias, JM [1 ]
Soudris, D [1 ]
机构
[1] UCM, DACYA, Madrid 28040, Spain
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Currently, portable consumer embedded devices are increasing more and more their capabilities and can now implement new algorithms (e.g. multimedia and wireless protocols) that a few years ago were reserved only for powerful workstations. Unfortunately, the original design characteristics of such applications do not often allow to port them directly in current embedded devices. These applications share complex and intensive memory use. Furthermore, they must heavily rely on dynamic memory due to the unpredictability of the input data (e.g. 3D streams features) and system behaviour (e.g. number of applications running concurrently defined by the user). Thus they require that the dynamic memory subsystem involved is able to provide the necessary level of performance for these new dynamic applications. However, actual embedded systems have very limited resources (e.g. speed and power consumed in the memory subsystem) to provide efficient general-purpose dynamic memory management. In this paper we propose a new methodology to design custom dynamic memory managers that provide the performance required in new embedded devices by reducing the amount of memory accesses to handle these new dynamic multimedia and wireless network applications. Our results in real-life dynamic applications show significant improvements in memory accesses of dynamic memory managers i.e. up to 58%, compared to state-of-the-art dynamic memory management solutions for complex applications.
引用
收藏
页码:93 / 98
页数:6
相关论文
共 50 条
  • [41] An assertion-based verification methodology for system-level design
    Gharehbaghi, Amir Masoud
    Yaran, Benyamin Hamdin
    Hessabi, Shaahin
    Goudarzi, Maziar
    COMPUTERS & ELECTRICAL ENGINEERING, 2007, 33 (04) : 269 - 284
  • [42] SPEED SYSTEM MEMORY BY INTERLEAVING DRAM ACCESSES
    MEKHIEL, N
    ELECTRONIC DESIGN, 1989, 37 (21) : 65 - &
  • [43] Dynamic Fine-Grained Sparse Memory Accesses
    Akin, Berkin
    Chou, Chiachen
    Park, Jongsoo
    Hughes, Christopher J.
    Agarwal, Rajat
    PROCEEDINGS OF THE INTERNATIONAL SYMPOSIUM ON MEMORY SYSTEMS (MEMSYS 2018), 2018, : 85 - 97
  • [44] AUTOMATIC GENERATION OF MAPS OF MEMORY ACCESSES FOR ENERGY-AWARE MEMORY MANAGEMENT
    Balasa, Florin
    Luican, Ilie I.
    Zhu, Hongwei
    Nasui, Doru V.
    2009 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOLS 1- 8, PROCEEDINGS, 2009, : 629 - +
  • [45] A high-level requirements engineering methodology for electronic system-level design
    Gorse, N.
    Belanger, P.
    Chureau, A.
    Aboulhamid, E. M.
    Savaria, Y.
    COMPUTERS & ELECTRICAL ENGINEERING, 2007, 33 (04) : 249 - 268
  • [46] A Methodology for Estimating Memory Lifetime Using a System-Level Accelerated Life Test and Error-Correcting Codes
    Kim, Dae-Hyun
    Milor, Linda
    2017 IEEE 35TH VLSI TEST SYMPOSIUM (VTS), 2017,
  • [47] SYSTEM-LEVEL DESIGN
    BOURBON, B
    COMPUTER DESIGN, 1990, 29 (23): : 19 - 21
  • [48] DyCache: Dynamic Multi-Grain Cache Management for Irregular Memory Accesses on GPU
    Guo, Hui
    Huang, Libo
    Lu, Yashuai
    Ma, Sheng
    Wang, Zhiying
    IEEE ACCESS, 2018, 6 : 38881 - 38891
  • [49] Methodology and experimental setup for the determination of system-level dynamic reconfiguration overhead
    Papadimitriou, Kyprianos
    Anyfantis, Antonis
    Dollas, Apostolos
    FCCM 2007: 15TH ANNUAL IEEE SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, PROCEEDINGS, 2007, : 335 - +
  • [50] Formal Model for System-Level Power Management Design
    Simonovic, Mirela
    Zivojnovic, Vojin
    Saranovac, Lazar
    PROCEEDINGS OF THE 2017 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2017, : 1599 - 1602