Design, Simulation and Analysis of 4 x 1 Mux at 90 nm CMOS Technology

Power and delay are regarded as the most fundamental design constraints that form the basis of comparative analysis of logic style implementation of any arbitrary circuit. Previously published research works and investigations have proposed various low power logic style implementations of 2:1 multiplexer circuits. This paper focuses on the design, simulation and analysis of 4:1 multiplexer circuit using CMOS, CVSL, PTL and dynamic logic styles at 90 nm technology followed by a comparison of the circuit performance w.r.t. power, delay and power-delay product. Further, based on this evaluation of circuit families; it has been shown that transmission gate (CMOS+) is the logic style of choice which is most optimized and efficient both in terms of power and speed within 1.6-2.4 V supply voltage range. The circuits have been designed and simulated using BSIM 3V3 90 nm technologies on Tanner EDA tool.