Design, Simulation and Analysis of Energy Efficient 1-Bit Full Adder at 90nm CMOS Technology for Deep Submicron Levels

被引：0

作者：

Jain, Rohan ^{[1
]}

Singh, Prateek ^{[1
]}

Sharma, Anmol ^{[1
]}

Sharma, Rajiv ^{[1
]}

机构：

[1] Northern India Engn Coll, Elect & Commun Dept, New Delhi, India

来源：

2016 IEEE INTERNATIONAL CONFERENCE ON COMPUTING, COMMUNICATION AND AUTOMATION (ICCCA) | 2016年

关键词：

full adder circuits; CPL; CMOS; power-delay product; energy efficient; hybrid full adder;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Previously published research works have proposed several designs for low power hybrid full adder cells and analyzed their power-delay performance against standard logic styles in various simulation environments. In this paper, a 1-bit energy efficient hybrid full adder cell has been proposed and its performance in terms of power, delay and power-delay product (PDP) has been compared with that of existing full adder cells designed and simulated using different CMOS logic styles. Results have shown that the proposed 12T hybrid full adder cell exhibits least power consumption and propagation delay in the voltage range of 0.8 volts to 2.4 volts. The circuits have been designed and simulated at 90nm BSIM 3v3 technology using Tanner EDA tool.

引用

页码：1444 / 1449

页数：6

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