Pseudo-Static 1T Capacitorless DRAM using 22nm FDSOI for Cryogenic Cache Memory

被引：7

作者：

Chakraborty, Wriddhi ^{[1
]}

Saligram, Rakshith ^{[2
]}

Gupta, Aniket ^{[1
]}

San Jose, Matthew ^{[1
]}

Aabrar, Khandker Akif ^{[1
]}

Dutta, Sourav ^{[1
]}

Khanna, Abhishek ^{[1
]}

Raychowdhury, Arijit ^{[2
]}

Datta, Suman ^{[1
]}

机构：

[1] Univ Notre Dame, Notre Dame, IN 46556 USA

[2] Georgia Inst Technol, Atlanta, GA 30332 USA

来源：

2021 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2021年

关键词：

D O I：

10.1109/IEDM19574.2021.9720578

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Cryogenic CMOS processors need low latency, high bandwidth access to high-density on-die cache memory to maximize performance. In this work, we experimentally demonstrate, for the first time, pseudo-static random access memory operation of a 1T Capacitorless Floating Body DRAM using 22nm FDSOI transistor, down to 4.8K, suitable for cryogenic cache memory. We demonstrate a 1T Cryo-DRAM (W/L-G =120nm/20nm) that exhibit : (a) record high sensing current and sense margin (Delta I-Read=I-Read,I-1-I-Read,I-0), (b) pseudo-static retention characteristics (>10(5) sec ); (c) high write endurance > 10(10) cycles, and (d) non-destructive read cycles > 10(16), suitable for cache application. Benchmarking reveals that 1T Cryo-DRAM outperforms Cryo-SRAM and Cryo-STT-MRAM in memory density by 10x and 50x; in read/write energy by 2.7x/2.4x and 1.3x/1.5x and in read latency by 1.46x and 1.80x respectively for a cache size of 2MB. Hence, 1T Cryo-DRAM is a viable option for L2/L3 cache in high-performance cryogenic computing.

引用

页数：4

共 15 条

[1] Capacitorless 1T Memory Cells Using Channel Traps at Grain Boundaries
Chen, Yen-Ting
Sun, Hung-Chang
Huang, Ching-Fang
Wu, Ting-Yun
Liu, C. W.
Hsu, Yuan-Jun
Chen, Jim-Shone
[J]. IEEE ELECTRON DEVICE LETTERS, 2010, 31 (10) : 1125 - 1127
[2] 1T-DRAM at the 22nm Technology Node and Beyond: an Alternative to DRAM with High-k Storage Capacitor
Bawedin, M.
Cristoloveanu, S.
Hubert, A.
Guegan, G.
Chang, S. J.
Sagnes, B.
Martinez, F.
Pascal, F.
Valenza, M.
Hoffmann, A.
[J]. 2011 14TH INTERNATIONAL SYMPOSIUM ON ELECTRETS (ISE), 2011, : 93 - +
[3] Low-Cost and Highly Heat Controllable Capacitorless PiFET (Partially Insulated FET) 1T DRAM for Embedded Memory
Bae, Dono-il
Kim, Sungho
Choi, Yang-Kyu
[J]. IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2009, 8 (01) : 100 - 105
[4] Novel Capacitorless 1T-DRAM Cell for 22-nm Node Compatible With Bulk and SOI Substrates
Rodriguez, Noel
Cristoloveanu, Sorin
Gamiz, Francisco
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2011, 58 (08) : 2371 - 2377
[5] Competitive 1T-DRAM in 28 nm FDSOI Technology for Low-Power Embedded Memory
El Dirani, H.
Bawedin, M.
Lee, K.
Parihar, M.
Mescot, X.
Fonteneau, P.
Galy, Ph.
Gamiz, F.
Kim, Y-T.
Ferrari, P.
Cristoloveanu, S.
[J]. 2016 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), 2016,
[6] 1T Non-Volatile Memory Design Using Sub-10nm Ferroelectric FETs
Sharma, Ankit
Roy, Kaushik
[J]. IEEE ELECTRON DEVICE LETTERS, 2018, 39 (03) : 359 - 362
[7] A design of a capacitorless 1T-DRAM cell using gate-induced drain leakage (GIDL) current for low-power and high-speed embedded memory
Yoshida, E
Tanaka, T
[J]. 2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, 2003, : 913 - 916
[8] A capacitorless 1T-DRAM technology using gate-induced drain-leakage (GIDL) current for low-power and high-speed embedded memory
Yoshida, E
Tanaka, T
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2006, 53 (04) : 692 - 697
[9] A 6T SRAM cell based Pipelined 2R/1W Memory Design using 28nm UTBB-FDSOI
Kaur, Ramandeep
Fell, Alexander
Rawat, Harsh
[J]. 2015 28TH IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC), 2015, : 310 - 315
[10] A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications
Somasekhar, D
Lu, SL
Bloechel, B
Dermer, G
Lai, K
Borkar, S
De, V
[J]. ESSCIRC 2005: PROCEEDINGS OF THE 31ST EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, 2005, : 355 - 358

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