Capacitorless 1T Memory Cells Using Channel Traps at Grain Boundaries

A capacitorless single-transistor (1T) memory cell with a long data-retention time is demonstrated on polycrystalline silicon thin-film transistors (TFTs). A new operation mode using channel traps is employed to modulate the drain current in the accumulation region. The different drain current can be read by modulating the barrier height at the grain boundary. The extrapolated retention time at the half of the current window is similar to 10(7) s. There is no degradation after 2000 write/erase cycles by trap-assisted tunneling programming. The low-temperature process of the TFT cells is attractive for the 3-D integration.