A High Speed Low-Power Accumulator for Direct Digital Frequency Synthesizer

被引：7
|
作者：
Kim, Yong Sin [1 ]
Kang, Sung-Mo [1 ]
机构：
[1] Univ Calif Santa Cruz, Dept Elect Engn, 1156 High St, Santa Cruz, CA 95064 USA
来源：
2006 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST, VOLS 1-5 | 2006年
关键词：
accumulator; direct digital frequency synthesizer (DDFS); gated clock; low power; pipelining;
D O I：
10.1109/MWSYM.2006.249620
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A high speed low-power 32-bit accumulator for direct digital frequency synthesizer (DDFS) is presented. The DDFS consists of a phase accumulator, a phase-to-sine amplitude converter, and a D/A converter. For accumulator design, high speed pipelining scheme is commonly used to increase throughput and to reduce power consumption. Our design decreases power consumption and the number of registers down to 24% and 37% of the conventional pipelined accumulator.
引用
收藏
页码：502 / 505
页数：4
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