Low-Power and High-SFDR Direct Digital Frequency Synthesizer Based on Hybrid CORDIC Algorithm

This paper describes the architecture and VLSI (very large scale integration) implementation of a direct digital frequency synthesizer (DDFS) based on a hybrid CORDIC (COordinate Rotation Digital Computer) algorithm. It is shown that the architecture can be implemented as a multiplier-less, small ROM (4 x 16 -bit) and pipelined data path. A SoC (system on chip) has been designed with 0/18 mu m 1P6M CMOS, and emulated on Xilinx FPGA (field programmable gate array). The proposed technique uses hybrid CORDIC algorithm of sine and cosine functions to achieve more than 84.4-dB(c) spurious free dynamic range (SFDR). The performances of novel DDFS based on hybrid CORDIC algorithm compares favorably with digital circuit design, power consumption and SFDR.