A low-power High-SFDR CMOS direct digital frequency synthesizer

被引：0
|
作者：
Wang, JS [1 ]
Lin, SJ [1 ]
Yeh, CW [1 ]
机构：
[1] Natl Chung Cheng Univ, Dept Elect Engn, Chiayi 621, Taiwan
来源：
2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS | 2005年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A low-power high-SFDR CMOS direct digital frequency synthesizer (DDFS) is presented. Several design techniques, including a cell-based lookup table, a power aware parameters selection method, a reduced multiplier, a speeded-up adder/subtracter, an extra pipeline stage, and supply voltage scaling, are used to make the design more easily synthesizable and much more power efficient. A synthesized 0.35-mu m DDFS, with an SFDR of -100 dBc, runs up to 100MHz and consumes only 26.2-mW with a supply voltage of 1.7V. The power efficiency is 0.26-mW/MHz, which represents an enhancement of more than 90% compared to the conventional DDFSs.
引用
收藏
页码：1670 / 1673
页数：4
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